Msr Bit Settings - IBM PowerPC 604 User Manual

Typically, when an exception occurs, bits 2-4 and 10--12 of SRRl are loaded with
exception-specific information and bits 5-9, and 16-31 of MSR are placed into the
corresponding bit positions of SRRl.
Note that in other implementations every instruction fetch that occurs when MSR[IR]
=
1,
and every instruction execution requiring address translation when MSR[DR]
=
1, may
modify SRRl.
In the 604 and in other 32-bit Power PC implementations, the MSR is 32 bits wide as shown
in Figure 4-3.
Iii
Reserved
:::::::::::::~:::::::::::::::::::t:::1:1:1:1iiii!i!i!iii!i~::::::::ii::::::::::::I::::,
POW
::M
ILE EE PR FP ME FEO SE BE FE1
:::~:::
IP IR D
I
PM RI LE
0 12 13 14 15 16 171819 20 2122 23 24 25262728293031
Figure 4-3. Machine State Register (MSR)
The MSR bits are defined in Table 4-3. Full function reserved bits are saved in SRRl when
an exception occurs; partial function reserved bits are not saved
Table 4-3. MSR Bit Settings
Blt(s) Name Description
0
-
Reserved. FuH Function.
1-4
-
Reserved. Partial function.
S-9
-
Reserved. FuU function.
10-12
-
Reserved. Partial function.
13
POW Power management enable
0
Power management disabled (normal operation mode).
1
Power management enabled (reduced power mode).
Note that power management functions are implementation-dependent.
14
-
Reserved-Implementation-specific
15
ILE Exception little-endian mode. When an exception occurs, this bit is copied into MSR(LE] to
select the endian mode for the context established by the exception.
16
EE External interrupt enable
0 WhHe the bit is cleared the processor delays recognition of external interrupts and
decrementer exception conditions.
1
The processor is enabled to take an external interrupt or the decrementer exception.
17
PR Privilege level
0
The processor can execute both user- and supervisor-level instructions.
1
The processor can only execute user-level instructions.
Chapter 4. Exceptions
4-7