Table of Contents
Advertisement
Development Capabilities and Interface
The instructions or data are then transferred in parallel to the core and TECR. When the
processor enters debug mode it fetches instructions from the DPIR, which causes an access
to the development interface port shift register. These instructions are serially loaded into
the shift register from the DSDI using DSCK or CLKOUT as the shift clock. Similarly, data is
transferred to the core. Data is shifted into the shift register and read by the processor when
a "move from special-purpose register DPDR" instruction is executed. Data is also parallel
loaded into the development interface port shift register from the core by executing a "move
to special-purpose register DPDR" instruction. It is then serially shifted out to the DSDO pin
using DSCK or CLKOUT as the shift clock.
20.4.3.5.2 Trap Enable Control Register. The 9-bit trap enable control register (TECR) is
loaded from the development interface port shift register. The content of the TECR drives
the six trap enable signals, two breakpoint signals, and the VSYNC signal to the core. The
transfer data to trap enable control register commands are used to force the appropriate bits
to be transferred to this register. The trap enable control register is not accessed by the core,
but supplies signals to the core. The trap enable bits, VSYNC bit, and the breakpoint bits of
this register are loaded from the development interface port shift register as a result of trap
enable mode transmissions. The trap enable bits are reflected in the ICTRL and LCTRL2
special registers. Refer to Section 20.6.2 Development Port Registers for more
information on the support registers.
20.4.3.5.3 Decoding the Development Interface Port Registers. The development
interface port shift register is selected when the core accesses the DPIR or DPDR registers.
Accesses to these two special-purpose registers occur in debug mode and appear on the
internal bus as an address and when an address attribute signal is asserted, a special-
purpose register is accessed. The DPIR is read by the core to fetch all instructions when in
debug mode. The DPDR is read and written to transfer data between the core and external
development tools. The DPIR and DPDR are pseudo-registers, so decoding either of these
registers causes the development interface port shift register to be accessed. The debug
mode logic knows whether the core is fetching instructions or reading or writing data. A
sequence error is signaled to the external development tool when the expected result of the
core and the GPR do not match. For example, when an instruction is received instead of the
expected data.
20.4.3.6 DEVELOPMENT PORT SERIAL COMMUNICATION. All serial transmissions
are synchronous, with respect to the transmission clock.
20.4.3.6.1 Clock Mode Selection. With the exception of CLKOUT, the transmission clock
can either be synchronous or asynchronous. The development port has two methods for
clocking serial transmissions. The first method allows the transmission to occur with no
external synchronization to CLKOUT. In this mode, a serial clock DSCK must be supplied
to the MPC823e. The other communication method requires data to be externally
synchronized.
MOTOROLA
MPC823e REFERENCE MANUAL
20-31
Advertisement
Table of Contents
