Motorola MPC823e Reference Manual page 1085

Development Capabilities and Interface
20.4.2.1 DEBUG MODE ENABLE VS. DEBUG MODE DISABLE. For protection
purposes, there are two possible working modes—debug mode enable and debug mode
disable. These modes are selected at reset. Debug mode is enabled by asserting the DSCK
pin during reset and the state of this pin is sampled three clocks before SRESET negation.
If the DSCK pin is sampled negated, debug mode is disabled until a subsequent reset that
occurs when the DSCK pin is asserted. When debug mode is disabled, the internal
watchpoint/breakpoint hardware is still operational and can be used by a software monitor
program for debugging purposes. A timing diagram for the enabling debug mode is
illustrated in Figure 20-7
Note: SRESET negation time depends on an external pull-up resistor, so any reference
to SRESET negation time refers to the time the MPC823e releases SRESET. If
the rise time of SRESET is long because of a large resistor, the setup time for
the debug port signals must be adjusted accordingly.
When debug mode is disabled, all development support registers are accessible when
MSR =0 and can be used by the monitor debugger software. However, the processor
PR
never enters debug mode and the ICR and DER are only used to assert or negate the freeze
signal. For more information on the software monitor debugger, refer to
Section 20.5 Software Monitor Debugger. Only when the core is in debug mode are all
development support registers accessible. Therefore, the development system has full
control of the core's development support features. For more information, see Table
20.4.2.2 ENTERING DEBUG MODE. Debug mode entry can be the result of a number of
events. All events have a programmable enable bit so you can discover the cause of debug
mode entry, as well as the events that require regular interrupt handling. By programming
the development port, you can enter debug mode immediately out of reset, thus allowing a
system to be debugged without ROM. If the DSCK pin is asserted during SRESET assertion
and after SRESET negation, the processor will take a breakpoint exception and go directly
to debug mode, instead of fetching the reset vector.
20-24 MPC823e REFERENCE MANUAL
20-12.
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