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20.4.3 The Development Interface Port
The development port provides a full-duplex serial interface for communication between the
internal development support logic and an external development tool. The relationship of the
development support logic to the rest of the core is illustrated in Figure 20-5 (page 20-21).
Notice that the development port support logic is shown as a separate block for clarity. It will
be implemented as part of the system interface unit module. The development interface port
contains four pins:
• Development serial clock
• Development serial data in
• Development serial data out
• Freeze
20.4.3.1 DEVELOPMENT SERIAL CLOCK. The development serial clock (DSCK) pin is
used to shift data into and out of the development interface port shift register. At the same
time, the new most-significant bit of the shift register is presented to the development serial
data out (DSDO) pin. Future references to the DSCK signal imply the internally
synchronized value of the clock. The DSCK input must be driven either high or low at all
times and is not allowed to float. With a resistor, a typical target environment would pull this
input low.
The clock can be implemented as a free-running or gated clock. The shifting of data is
controlled by the ready and start signals, so the clock does not need to be gated with the
serial transmissions. The DSCK pin is used at reset to enable debug mode immediately
following reset or when driving an event.
20.4.3.2 DEVELOPMENT SERIAL DATA IN. Data to be transferred into the development
interface port shift register is presented to the development serial data in (DSDI) pin by
external logic. When driven asynchronous with the system clock, the data presented to the
DSDI pin must be stable at setup time before the rising edge of DSCK and at hold time after
the rising edge of DSCK. When synchronously driven to the system clock, the data must be
stable on DSDI or a setup time before a system clock output (CLKOUT) rising edge and a
hold time after the rising edge of CLKOUT. The DSDI pin is also used at reset to control the
overall chip configuration mode and to determine the development port clock mode. Refer
to Section 20.4.3.6 Development Port Serial Communication for more information.
20.4.3.3 DEVELOPMENT SERIAL DATA OUT. The debug mode logic shifts data out of
the development interface port shift register using the development serial data out (DSDO)
pin. All transitions on DSDO are synchronous with DSCK or CLKOUT, depending on the
clock mode. Data will be valid at setup time before the rising edge of the clock and remains
valid at hold time after the rising edge of the clock. See Table 20-10 for details about DSDO
data.
MOTOROLA
Development Capabilities and Interface
MPC823e REFERENCE MANUAL
20-29
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