Spi Interface; Mdi Interface; Figure 4-18. Mss Spi Interface - Texas Instruments AM273 Series User Manual

Evaluation module

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Hardware Description

4.9 SPI Interface

The EVM supports four SPIs:

•

Two main subsystem interfaces:

– MSS_SPIA is accessible through the FTDI USB port (J10) via the FT4232HL UART USB bridge.

– MSS_SPIB is multiplexed out via the TS3A5018RSVR multiplexor to either the PMIC and debug test pins

(J16) or the 60 Pin Debug Header (J7). The TS3A5018RSVR mutliplexor is driven by S2 which acts as

a select line. When set to 'PMIC_SPI' position, the MSS_SPIB interface is routed to the PMIC and J16

header. When set to 'DBG_SPI', the MSS_SPIB interface is routed to the 60-pin debug header (J7). The

CS1 line of the MSS_SPIB interface bypasses the multiplexor and is routed directly to the 60 Pin Debug

Header.

•

Two radar control subsystem interfaces:

– RCSS_SPIA is routed to the HD front end connector J1.

– RCSS_SPIB is routed to the HD front end connector J11.

The AM273x EVM has a two signal (clock and data) MDI interface. This purpose of the interface is to configure

the Ethernet PHY. Since a PHY (TI's DP83867ERGZR) is established for the EVM, the software of the EVM is

set to properly configure this PHY by default.

Please refer to

Figure 4-5

AM273x Evaluation Module

for more detail on the Ethernet PHY design.

SPRUIY1B – NOVEMBER 2020 – REVISED FEBRUARY 2024

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