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2.8
DSD Output Mode Configuration
The PCM4222 supports a one-bit Direct Stream Digital (DSD) data output, which operates at either 64x or
128x the base PCM output sampling rate. The PCM4222 allows both the DSD and PCM output modes to
be enabled simultaneously. The DSD data for the left and right channels and the associated bit clock are
output at the DSD data port, or header J5.
Header J5 Pin Number
The DSD output mode is enabled or disabled using the DSDEN input (pin 22). This input is controlled via
the DSDEN element on switch SW1.
output is disabled, DSDCLK (pin 27), DSDL (pin 28), and DSDR (pin 29) are forced low.
Switch SW1, DSDEN
The DSD output data rate may be set to 64x or 128x the base PCM rate (typically 44.1kHz). The output
rate is selected via the DSDMODE input (pin 24). This input is controlled via the DSDMODE element on
switch SW1.
Table 20
Switch SW1, DSDMODE
For more information regarding DSD output mode operation, timing, and specifications, see the
datasheet.
SBAU124 – December 2006
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Table 18
Table 18. DSD Data Port Header Pin Configuration
1
3
5
2,4,6,7,8,9,10
Table 19
Table 19. DSD Output Mode Configuration
LO
HI
summarizes the operation of this switch.
Table 20. DSD Output Rate Selection
LO
HI
lists the pin configuration for header J5.
DSD Data Port Signal Name, Description
DSDCLK, DSD Bit Clock Output
DSDL, One-bit DSD Data Output for the Left Channel
DSDR, One-bit DSD Data Output for the Right Channel
summarizes the operation of this switch. When the DSD
DSD Output Mode
DSD Output Data Rate
64x Oversampled Data with Output Rate = MCKI ÷ 4
128x Oversampled Data with Output Rate = MCKI ÷ 2
Hardware Configuration
Ground
Disabled
Enabled
PCM4222
PCM4222EVM User's Guide
15
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