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Schematic
J21 and J27
0 V to 50 V
0A to 5A
TP19
J21
VIN_KVU3
VIN_KVU3
J25
J23
0 V to 100 V
1
0A to 5A
DNP
DNP
J25
2
1
TP20
J27
GND_KVU3
GND_KVU3
18
MLTLDO2EVM-037 Evaluation Module
U3
VIN_KVU3
1
VI
C24
C25
DNP
DNP
C28
C29
C30
100uF
47µF
TPS7B8850QKVURQ1
100nF
1uF
1uF
VIN_KVU3
GND_KVU3
VOUT_KVU3
Figure 8. Generic 3-pin KVU Package Schematic
Copyright © 2020, Texas Instruments Incorporated
3
VOUT_KVU3
VO
DNP
4
GND_KVU3
PAD
C31
100nF
J29
1
2
3
4
DNP
5
6
GND_KVU3
J24
1
C26
C27
C32
DNP
C33
DNP
DNP
47µF
100µF
DNP
10uF
1uF
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J22 and J28
0 V to 50 V
TP18
0A to 5A
J22
VOUT_KVU3
VOUT_KVU3
J26
0 V to 100 V
0A to 5A
J26
1
2
TP21
J28
GND_KVU3
SBVU065 – May 2020
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