Block Diagram - Texas Instruments SimpleLink CC2620 Technical Reference Manual

Block Diagram

19.2 Block Diagram
Figure 19-1 shows the UART module block diagram.
PERDMACLK
DMA Request
Interrupt
Identification regiters
Control / Status
UART_PERIPHID0
UART_PERIPHID1
UART_PERIPHID2
UART_PERIPHID3
Control / Status
UART_PCELLID0
UART_PCELLID1
UART_PCELLID2
UART_PCELLID3
19.3 Signal Description
Table 19-1 lists the external signals of the UART module and describes the function of each. The UART
signals are set in the IOCFGn registers. For more information on configuring GPIOs, see
Control chapter.
Pin Name
UARTRxD
UARTTxD

(1)

I = Input; O = Output; I/O = Bidirectional
19.4 Functional Description
Each CC26xx and CC13xx UART performs the functions of parallel-to-serial and serial-to-parallel
conversions. The CC26xx and CC13xx UART is similar in functionality to a 16C550 UART, but is not
register compatible.
The UART is configured for transmit and receive through the UART Control Register (UART:CTL) TXE
and RXE bits. Transmit and receive are both enabled out of reset. Before any control registers are
programmed, the UART must be disabled by clearing the UART:CTL UARTEN register bit. If the UART is
disabled during a transmit or receive operation, the current transaction completes before the UART stops.
1340
Universal Asynchronous Receivers and Transmitters (UARTS)
Figure 19-1. UART Module Block Diagram
Clock control
UART_CTL
DMA control
UART_DMACTL
Interrupt control
UART_IFLS
UART_IMSC
UART_MIS
UART_RIS
UART_ICR
UART_DR
Control / Status
Control / Status
UART_RSR/ECR
UART_FR
UART_LCRH
UART_CTL
Table 19-1. Signals for UART
Pin Number Pin Type
Assigned through I
GPIO
O
configuration
Copyright © 2015, Texas Instruments Incorporated
TX FIFO
32 x 8
Baud rate
generator
UART_IBRD
UART_FBRD
RX FIFO
32 x 12
(1)
Description
UART module 0 receive
UART module 0 transmit
SWCU117C – February 2015 – Revised September 2015
www.ti.com
UARTTXD
Transmitter
UARTRXD
Receiver
Chapter 11, I/O
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