Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1093

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13.5.1.2 TAMR Register (Offset = 4h) [reset = 0h]
TAMR is shown in
Timer A Mode
31 30
23 22
15 14
TCACT
R/W-0h
7 6
TASNAPS TAWOT
R/W-0h R/W-0h
Bit Field
31-16 RESERVED
15-13 TCACT
12 TACINTD
11 TAPLO
10 TAMRSU
9 TAPWMIE
SWCU117C – February 2015 – Revised September 2015
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Figure 13-10 and described in
Figure 13-10. TAMR Register
29 28
21 20
13 12
TACINTD
R/W-0h
5 4
TAMIE TACDIR
R/W-0h R/W-0h
Table 13-9. TAMR Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 13-9.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
TAPLO TAMRSU
R/W-0h R/W-0h
3
TAAMS TACM
R/W-0h R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Timer Compare Action Select
0h = DIS_CMP : Disable compare operations
1h = Toggle State on Time-Out
2h = Clear CCP output pin on Time-Out
3h = Set CCP output pin on Time-Out
4h = Set CCP output pin immediately and toggle on Time-Out
5h = Clear CCP output pin immediately and toggle on Time-Out
6h = Set CCP output pin immediately and clear on Time-Out
7h = Clear CCP output pin immediately and set on Time-Out
One-Shot/Periodic Interrupt Disable
0h = Time-out interrupt function as normal
1h = Time-out interrupt are disabled
Legacy PWM operation
0h = Legacy operation
1h = CCP output pin is set to 1 on time-out
Timer A Match Register Update mode
This bit defines when the TAMATCHR and TAPR registers are
updated.
If the timer is disabled (CTL.TAEN = 0) when this bit is set,
TAMATCHR and TAPR are updated when the timer is enabled.
If the timer is stalled (CTL.TASTALL = 1) when this bit is set,
TAMATCHR and TAPR are updated according to the configuration
of this bit.
0h = Update TAMATCHR and TAPR, if used, on the next cycle.
1h = Update TAMATCHR and TAPR, if used, on the next time-out.
GPT Timer A PWM Interrupt Enable. This bit enables interrupts in
PWM mode on rising, falling, or both edges of the CCP output.
0h = Interrupt is disabled.
1h = Interrupt is enabled. This bit is only valid in PWM mode.
General-purpose Timer Registers
26 25
18 17
10 9
TAPWMIE
R/W-0h
2 1
TAMR
R/W-0h
Timers
24
16
8
TAILD
R/W-0h
0
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