Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1354

UARTS Registers
19.7.1.6 FBRD Register (Offset = 28h) [reset = 0h]
FBRD is shown in
Fractional Baud-Rate Divisor
If this register is modified while transmission or reception is on-going, the baud rate will not be updated
until transmission or reception of the current character is complete.
31 30 29 28
15 14 13 12
Bit Field
31-6 RESERVED
5-0 DIVFRAC
1354
Universal Asynchronous Receivers and Transmitters (UARTS)
Figure 19-9 and described in
Figure 19-9. FBRD Register
27 26 25
11 10 9
RESERVED
R/W-0h
Table 19-9. FBRD Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 19-9.
24 23 22 21
RESERVED
R/W-0h
8 7 6 5
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Fractional Baud-Rate Divisor:
The baud rate divisor is calculated using the formula below:
Baud rate divisor = (UART reference clock frequency) / (16 * Baud
rate)
Baud rate divisor must be minimum 1 and maximum 65535.
That is, IBRD.DIVINT=0 does not give a valid baud rate.
Similarly, if IBRD.DIVINT=0xFFFF, any nonzero values in DIVFRAC
will be illegal.
A valid value must be written to this field before the UART can be
used for RX or TX operations.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
20 19 18 17
4 3 2 1
DIVFRAC
R/W-0h
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