Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1391

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20.7.1.8 MIS Register (Offset = 1Ch) [reset = 0h]
MIS is shown in Figure 20-20
Masked Interrupt Status
31 30
23 22
15 14
7 6
RESERVED
Bit Field
31-4 RESERVED
3 TXMIS
2 RXMIS
1 RTMIS
0 RORMIS
SWCU117C – February 2015 – Revised September 2015
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and described in
Figure 20-20. MIS Register
29 28
21 20
13 12
5 4
R-0h
Table 20-10. MIS Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 20-10.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
TXMIS RXMIS
R-0h R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Masked interrupt state of transmit FIFO interrupt:
This field returns the masked interrupt state of transmit FIFO
interrupt which is the AND product of raw interrupt state RIS.TXRIS
and the mask setting IMSC.TXIM.
Masked interrupt state of receive FIFO interrupt:
This field returns the masked interrupt state of receive FIFO interrupt
which is the AND product of raw interrupt state RIS.RXRIS and the
mask setting IMSC.RXIM.
Masked interrupt state of receive timeout interrupt:
This field returns the masked interrupt state of receive timeout
interrupt which is the AND product of raw interrupt state RIS.RTRIS
and the mask setting IMSC.RTIM.
Masked interrupt state of receive overrun interrupt:
This field returns the masked interrupt state of receive overrun
interrupt which is the AND product of raw interrupt state
RIS.RORRIS and the mask setting IMSC.RORIM.
SSI Registers
26 25
18 17
10 9
2 1
RTMIS
R-0h
Synchronous Serial Interface (SSI)
24
16
8
0
RORMIS
R-0h
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