Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1444

I2S Registers
22.10.1.4 AIFFMTCFG Register (Offset = Ch) [reset = 170h]
AIFFMTCFG is shown in
Serial Interface Format Configuration
31 30
23 22
15 14
7 6
MEM_LEN_24 SMPL_EDGE
R/W-0h R/W-1h
Bit Field
31-16 RESERVED
15-8 DATA_DELAY
7 MEM_LEN_24
6 SMPL_EDGE
5 DUAL_PHASE
4-0 WORD_LEN
1444
Integrated Interchip Sound (I2S) Module
Figure 22-12 and described in
Figure 22-12. AIFFMTCFG Register
29 28
RESERVED
21 20
RESERVED
13 12
DATA_DELAY
R/W-1h
5 4
DUAL_PHASE
R/W-1h
Table 22-5. AIFFMTCFG Register Field Descriptions
Type Reset
R 0h
R/W 1h
R/W 0h
R/W 1h
R/W 1h
R/W 10h
Copyright © 2015, Texas Instruments Incorporated
Table 22-5.
27 26
R-0h
19 18
R-0h
11 10
3 2
WORD_LEN
R/W-10h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
The number of BCLK periods between a WCLK edge and MSB of
the first word in a phase:
0x00: LJF format
0x01: I2S and DSP format
0x02: RJF format
...
0xFF: RJF format
Note: When 0, MSB of the next word will be output in the idle period
between LSB of the previous word and the start of the next word.
Otherwise logical 0 will be output until the data delay has expired.
The size of each word stored to or loaded from memory:
0h = 16BIT : 16-bit (one 16 bit access per sample)
1h = 24BIT : 24-bit (one 8 bit and one 16 bit locked access per
sample)
On the serial audio interface, data (and wclk) is sampled and
clocked out on opposite edges of BCLK.
0h = Data is sampled on the negative edge and clocked out on the
positive edge.
1h = Data is sampled on the positive edge and clocked out on the
negative edge.
Selects dual- or single-phase format.
0: Single-phase
1: Dual-phase
Number of bits per word (8-24):
In single-phase format, this is the exact number of bits per word.
In dual-phase format, this is the maximum number of bits per word.
Values below 8 and above 24 give undefined behavior. Data written
to memory is always aligned to 16 or 24 bits as defined by
MEM_LEN_24. Bit widths that differ from this alignment will either be
truncated or zero padded.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
9 8
1 0
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