Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1080

Functional Description
13.3.2.1 One-shot or Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the GPTM Timer n Mode
Register (GPT:TnMR) TnMR field. The timer is configured to count up or down using the GPT:TnMR
TnCDIR bit.
When software sets the GPTM Control Register (GPTIMER:CTL) TnEN bit, the timer begins counting up
from 0x0, or down from its preloaded value. Alternatively, if the GPT:TnMR register TnWOT bit is set when
the TnEN bit is set, the timer waits for a trigger to begin counting (see
Mode).
When the timer is counting down and reaches the time-out event (0x0), the timer reloads its start value
from the GPT:TnILR and the GPT:TnPR registers on the next cycle. When the timer is counting up and
reaches the time-out event (the value in the GPT:TnILR and the optional GPT:TnPR registers), the timer
reloads with 0x0. If configured to be a one-shot timer, the timer stops counting and clears the GPT:CTL
TnEN register bit. If configured as a periodic timer, the timer starts counting again on the next cycle. In
periodic snap-shot mode (the TnMR field is 0x2 and the GPT:TnMR TnSNAPS register bit is set), the
actual free-running value of the timer at the time-out event is loaded into the GPT:TnR register. In this
manner, software can determine the time elapsed from the interrupt assertion to the ISR entry by
examining the snapshot values and the current value of the free-running timer, which is stored in the
GPT:TnV register. Snapshot mode is not available when the timer is configured in one-shot mode.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the
time-out event. The GPTM sets the GPTM Raw Interrupt Status Register (GPT:RIS) TnTORIS bit, and
holds the bit until it is cleared by writing the GPTM Interrupt Clear Register (GPT:ICR). If the time-out
interrupt is enabled in the GPTM Interrupt Mask Register (GPT:IMR), the GPTM also sets the GPTM
Masked Interrupt Status Register (GPT:MIS) TnTOMIS bit. By setting the GPT:TnMR TnMIE register bit,
an interrupt condition can also be generated when the timer value equals the value loaded into the GPTM
Timer n Match Register (GPT:TnMATCHR) and the GPTM Timer n Prescale Match Register
(GPT:TnPMR). This interrupt has the same status, masking, and clearing functions as the time-out
interrupt but uses the match interrupt bits instead (for example, the raw interrupt status is monitored
through the GPTM Raw Interrupt Status Register (GPT:RIS) TnMRIS bit). The interrupt status bits are not
updated by the hardware unless the GPT:TnMR TnMIE register bit is set, which is different than the
behavior for the time-out interrupt.
If software updates the GPT:TnILR or the GPT:TnPR registers while the counter is counting down, the
counter loads the new value on the next clock cycle and continues counting from the new value if the
GPT:TnMR TnILD register bit is clear. If the TnILD bit is set, the counter loads the new value after the
next time out. If software updates the GPT:TnILR register or the GPT:TnPR register while the counter is
counting up, the time-out event is changed on the next cycle to the new value. If software updates the
GPTM Timer n Value Register (GPT:TnV) while the counter is counting up or down, the counter loads the
new value on the next clock cycle and continues counting from the new value. If software updates the
GPT:TnMATCHR register or the GPT:TnPMR register while the counter is counting, the match registers
reflect the new values on the next clock cycle if the GPT:TnMR TnMRSU register bit is clear. If the
TnMRSU bit is set, the new value does not take effect until the next time out.
If the GPT:CTL TnSTALL register bit is set, the timer freezes counting while the processor is halted by the
debugger. The timer resumes counting when the processor resumes execution.
Table 13-2 lists a variety of configurations for a 16-bit free-running timer while using the prescaler. All
values assume a 24-MHz clock with Tc = 41.67 ns (clock period). The prescaler can only be used when a
16- or 32-bit timer is configured in 16-bit mode.
1080 Timers
Copyright © 2015, Texas Instruments Incorporated
Section 13.3.3, Wait-for-Trigger
SWCU117C – February 2015 – Revised September 2015
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