Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1367

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19.7.1.14 DMACTL Register (Offset = 48h) [reset = 0h]
DMACTL is shown in
DMA Control
31 30
23 22
15 14
7 6
Bit Field
31-3 RESERVED
2 DMAONERR
1 TXDMAE
0 RXDMAE
SWCU117C – February 2015 – Revised September 2015
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Figure 19-17 and described in
Figure 19-17. DMACTL Register
29 28
RESERVED
21 20
RESERVED
13 12
RESERVED
5 4
RESERVED
R/W-0h
Table 19-17. DMACTL Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 19-17.
27 26
R/W-0h
19 18
R/W-0h
11 10
R/W-0h
3 2
DMAONERR
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
DMA on error. If this bit is set to 1, the DMA receive request outputs
(for single and burst requests) are disabled when the UART error
interrupt is asserted (more specifically if any of the error interrupts
RIS.PERIS, RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted).
Transmit DMA enable. If this bit is set to 1, DMA for the transmit
FIFO is enabled.
Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO
is enabled.
Universal Asynchronous Receivers and Transmitters (UARTS)
UARTS Registers
25 24
17 16
9 8
1 0
TXDMAE RXDMAE
R/W-0h R/W-0h
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