Texas Instruments SimpleLink CC2620 Technical Reference Manual page 870

Zigbee rf4ce wireless mcu simplelink cc13 series; simplelink cc26 series

Cryptography Registers

10.2.1.39 IRQSTAT Register (Offset = 790h) [reset = 0h]

IRQSTAT is shown in

Interrupt Status

KEY_ST_WR_ KEY_ST_RD_E

KEY_ST_WR_ERR

KEY_ST_RD_ERR

RESULT_AVAIL

Figure 10-41

and described in

Figure 10-41. IRQSTAT Register

Table 10-49. IRQSTAT Register Field Descriptions

This bit is set when a DMA bus error is detected during a DMA

operation. The value of this register is held until it is cleared through

IRQCLR.DMA_BUS_ERR

Note: This error is asserted if an error is detected on the AHB master

interface during a DMA operation.

Note: This is not an interrupt source.

This bit is set when a write error is detected during the DMA write

operation to the key store memory. The value of this register is held

until it is cleared through IRQCLR.KEY_ST_WR_ERR

Note: This error is asserted if a DMA operation does not cover a full

key area or more areas are written than expected.

Note: This is not an interrupt source.

This bit will be set when a read error is detected during the read of a

key from the key store, while copying it to the AES engine. The value

of this register is held until it is cleared through

IRQCLR.KEY_ST_RD_ERR.

Note: This error is asserted if a key location is selected in the key

store that is not available.

Note: This is not an interrupt source.

Software must not rely on the value of a reserved. Writing any other

value than the reset value may result in undefined behavior.

This bit returns the status of DMA data in done interrupt.

This bit is set high when the Crypto peripheral has a result available.

SWCU117C – February 2015 – Revised September 2015

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