Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1098

General-purpose Timer Registers
Bit Field
3-2 TAEVENT
1 TASTALL
0 TAEN
1098
Timers
Table 13-11. CTL Register Field Descriptions (continued)
Type Reset
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Description
GPT Timer A Event Mode
0h = Positive edge
1h = Negative edge
3h = Both edges
GPT Timer A Stall Enable
0h = Timer A continues counting while the processor is halted by the
debugger.
1h = Timer A freezes counting while the processor is halted by the
debugger.
GPT Timer A Enable
0h = Timer A is disabled.
1h = Timer A is enabled and begins counting or the capture logic is
enabled based on the CFG register.
SWCU117C – February 2015 – Revised September 2015
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