Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1416

2
I C Registers
21.5.1.8 SICR Register (Offset = 18h) [reset = 0h]
SICR is shown in Figure 21-21
Slave Interrupt Clear
This register clears the raw interrupt SRIS.
31 30
23 22
15 14
7 6
Bit Field
31-3 RESERVED
2 STOPIC
1 STARTIC
0 DATAIC
1416
Inter-Integrated Circuit (I
and described in
Figure 21-21. SICR Register
29 28
21 20
13 12
5 4
RESERVED
W-0h
Table 21-10. SICR Register Field Descriptions
Type Reset
W 0h
W 0h
W 0h
W 0h
2
C) Interface
Copyright © 2015, Texas Instruments Incorporated
Table 21-10.
27
RESERVED
W-0h
19
RESERVED
W-0h
11
RESERVED
W-0h
3
STOPIC
W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Stop condition interrupt clear
Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS.
Start condition interrupt clear
Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS.
Data interrupt clear
Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS.
SWCU117C – February 2015 – Revised September 2015
26 25
18 17
10 9
2 1
STARTIC
W-0h
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24
16
8
0
DATAIC
W-0h