Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1379

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In this configuration, the following occurs during idle periods:
• SSIn_CLK is forced low
• SSIn_FSS is forced high
• The transmit data line SSIn_TX is arbitrarily forced low
Writing a control byte to the TX FIFO triggers a transmission. The falling edge of SSIn_FSS transfers the
value in the bottom entry of the TX FIFO to the serial shift register of the transmit logic and shifts the MSB
of the 8-bit control frame out onto the SSIn_TX pin. SSIn_FSS remains low for the duration of the frame
transmission. The SSIn_RX pin remains 3-stated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on each rising edge of
SSIn_CLK. After the last bit is latched by the slave device, the control byte is decoded during a one clock
wait state and the slave responds by transmitting data back to the SSI. Each bit is driven onto the
SSIn_RX line on the falling edge of SSIn_CLK. The SSI latches each bit on the rising edge of SSIn_CLK.
At the end of the frame for single transfers, the SSIFss signal is pulled high one clock period after the last
bit is latched in the receive serial shifter transferring the data to the RX FIFO.
NOTE: The off-chip slave device can 3-state the receive line either on the falling edge of SSIn_CLK
after the LSB has been latched by the receive shifter or when the SSIn_FSS pin goes high.
For continuous transfers, data transmission begins and ends like a single transfer, but the SSIn_FSS line
is held low and data transmits back-to-back. The control byte of the next frame follows the LSB of the
received data from the current frame. After the LSB of the frame is latched into the SSI, each received
value is transferred from the receive shifter on the falling edge of SSIn_CLK.
Figure 20-11. MICROWIRE Frame Format (Continuous Transfer)
SSIn_Clk
SSIn_Fss
SSIn_Tx
SSIn_Rx
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIn_CLK after SSIFss has gone low. Masters driving a free-running SSIn_CLK must ensure that the
SSIFss signal has sufficient setup and hold margins compared to the rising edge of SSIn_CLK.
Figure 20-12 shows these setup and hold time requirements. With respect to the SSIn_CLK rising edge on
which the first bit of receive data is to be sampled by the SSI slave, SSIn_FSS must have a setup of at
least two times the period of SSIn_CLK on which the SSI operates. With respect to the SSIn_CLK rising
edge previous to this edge, SSIn_FSS must have a hold of at least one SSIn_CLK period.
Figure 20-12. MICROWIRE Frame Format, SSIFss Input Setup, and Hold Requirements
SWCU117C – February 2015 – Revised September 2015
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LSB MSB
0 MSB
LSB
4 to 16 bits
output data
SSIn_Clk
SSIn_Fss
SSIn_Rx
Copyright © 2015, Texas Instruments Incorporated
LSB
8-bit control
t =(2*t )
Setup SSIn_Clk
t =t
Hold SSIn_Clk
First RX data to besampled by SSI slave
Synchronous Serial Interface (SSI)
Functional Description
MSB
1379