Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1152

Watchdog Timer Registers
15.4.1.5 RIS Register (Offset = 10h) [reset = 0h]
RIS is shown in Figure 15-6
Raw Interrupt Status
31 30
23 22
15 14
7 6
Bit Field
31-1 RESERVED
0 WDTRIS
1152
Watchdog Timer
and described in Table 15-6.
Figure 15-6. RIS Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 15-6. RIS Register Field Descriptions
Type Reset Description
R 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R 0h This register is the raw interrupt status register. WDT interrupt
events can be monitored via this register if the controller interrupt is
masked.
Value Description
0: The WDT has not timed out
1: A WDT time-out event has occurred
Copyright © 2015, Texas Instruments Incorporated
27 26
19 18
11 10
3 2
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
www.ti.com
25 24
17 16
9 8
1 0
WDTRIS
R-0h