Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1102

General-purpose Timer Registers
13.5.1.7 RIS Register (Offset = 1Ch) [reset = 0h]
RIS is shown in Figure 13-15
Raw Interrupt Status
Associated registers:
IMR, MIS, ICLR
31 30
23 22
15 14
RESERVED
R-0h
7 6
RESERVED
R-0h
Bit Field
31-17 RESERVED
16 WURIS
15-14 RESERVED
13 DMABRIS
12 RESERVED
11 TBMRIS
10 CBERIS
9 CBMRIS
8 TBTORIS
1102
Timers
and described in Table
Figure 13-15. RIS Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
DMABRIS RESERVED
R-0h R-0h
5 4
DMAARIS TAMRIS
R-0h R-0h
Table 13-14. RIS Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
13-14.
27 26
19 18
11 10
TBMRIS CBERIS
R-0h R-0h
3 2
RTCRIS CAERIS
R-0h R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
GPT Write Update Error Raw Interrupt
0: No error.
1: Either Timer A or B was written twice in a Row or Timer A was
written before the corresponding Timer B was written.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
GPT Timer B DMA Done Raw Interrupt Status
0: Transfer has not completed
1: Transfer has completed
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
GPT Timer B Match Raw Interrupt
0: The match value has not been reached
1: The match value is reached.
TBMR.TBMIE is set, and the match values in TBMATCHR and
optionally TBPMR have been reached when configured in one-shot
or periodic mode.
GPT Timer B Capture Mode Event Raw Interrupt
0: The event has not occured.
1: The event has occured.
This interrupt asserts when the subtimer is configured in Input Edge-
Time mode
GPT Timer B Capture Mode Match Raw Interrupt
0: Match for Timer B has not occured
1: Match for Timer B has occurred.
This interrupt asserts when the values in the TBR and TBPR match
values in the TBMATCHR and TBPMR, and when configured in
Input Edge-Time mode (reg-ref instead!!)
GPT Timer B Time-out Raw Interrupt
0: Timer B has not timed out
1: Timer B has timed out.
This interrupt is asserted when a one-shot or periodic mode timer
reaches its count limit. The count limit is 0 or the value loaded into
TBILR, depending on the count direction.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
WURIS
R-0h
9 8
CBMRIS TBTORIS
R-0h R-0h
1 0
CAMRIS TATORIS
R-0h R-0h
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