Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1063

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12.5.1.7 SETBURST Register (Offset = 18h) [reset = 0h]
SETBURST is shown in
Channel Set UseBurst
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-0 CHNLS
SWCU117C – February 2015 – Revised September 2015
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Figure 12-13 and described in
Figure 12-13. SETBURST Register
CHNLS
R/W-0h
Table 12-14. SETBURST Register Field Descriptions
Type Reset
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 12-14.
9
Description
Returns the useburst status, or disables individual channels from
generating single uDMA requests. The value R is the arbitration rate
and stored in the controller data structure.
Read as:
Bit [Ch] = 0: uDMA channel Ch responds to both burst and single
requests on channel C. The controller performs 2
transfers.
Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer
requests. The controller only responds to burst transfer requests and
R
performs 2 transfers.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch]
to 0.
Bit [Ch] = 1: Disables single transfer requests on channel Ch. The
R
controller performs 2 transfers for burst requests.
Writing to a bit where a uDMA channel is not implemented has no
effect
Micro Direct Memory Access (µDMA)
µDMA Registers
8 7 6 5 4 3 2 1
R
, or single, bus
0
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