Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1392

SSI Registers
20.7.1.9 ICR Register (Offset = 20h) [reset = 0h]
ICR is shown in Figure 20-21
Interrupt Clear
On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
31 30
23 22
15 14
7 6
Bit Field
31-2 RESERVED
1 RTIC
0 RORIC
1392
Synchronous Serial Interface (SSI)
and described in Table
Figure 20-21. ICR Register
29 28
RESERVED
W-0h
21 20
RESERVED
W-0h
13 12
RESERVED
W-0h
5 4
RESERVED
W-0h
Table 20-11. ICR Register Field Descriptions
Type Reset Description
W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
W 0h Clear the receive timeout interrupt:
Writing 1 to this field clears the timeout interrupt (RIS.RTRIS).
Writing 0 has no effect.
W 0h Clear the receive overrun interrupt:
Writing 1 to this field clears the overrun error interrupt
(RIS.RORRIS). Writing 0 has no effect.
Copyright © 2015, Texas Instruments Incorporated
20-11.
27 26
19 18
11 10
3 2
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
9 8
1 0
RTIC RORIC
W-0h W-0h
Submit Documentation Feedback