Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1401

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Idle
Write slave
address to
I2C_MSA
Read I2C_MSTAT
BUSY bit = 0?
No
Yes
Write 0 J 111 to
I2C_MCTRL
Read I2C_MSTAT
BUSY bit = 0?
No
SWCU117C – February 2015 – Revised September 2015
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Figure 21-8. Master Single RECEIVE
Sequence may be omitted in
a single master system.
Error service
No
ERR bit = 0?
Yes
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Read data from
I2C_MDR
Yes
Inter-Integrated Circuit (I
Functional Description
Idle
1401
2
C) Interface