Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1348

UARTS Registers
19.7.1.1 DR Register (Offset = 0h) [reset = X]
DR is shown in Figure 19-4
Data
Words are transmitted:
• if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit
FIFO
• if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the
bottom word of the transmit FIFO).
• The write operation initiates transmission from the UART. The data is prefixed with a start bit,
appended with the appropriate parity bit (if parity is enabled), and a stop bit.
The resultant word is then transmitted.
Words are received:
• if the FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and
overrun) is pushed onto the 12-bit wide receive FIFO
• if the FIFOs are not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving
holding register (the bottom word of the receive FIFO).
The received data byte is read by performing reads from this register along with the corresponding status
information. The status information can also be read by a read of the RSR register.
31 30 29 28
15 14 13 12
RESERVED
R-0h
Bit Field
31-12 RESERVED
11 OE
10 BE
9 PE
1348
Universal Asynchronous Receivers and Transmitters (UARTS)
and described in Table
Figure 19-4. DR Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
OE BE PE FE
R-X R-X R-X R-X
Table 19-4. DR Register Field Descriptions
Type Reset
R 0h
R X
R X
R X
Copyright © 2015, Texas Instruments Incorporated
19-4.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
UART Overrun Error:
This bit is set to 1 if data is received and the receive FIFO is already
full. The FIFO contents remain valid because no more data is written
when the FIFO is full, , only the contents of the shift register are
overwritten.
This is cleared to 0 once there is an empty space in the FIFO and a
new character can be written to it.
UART Break Error:
This bit is set to 1 if a break condition was detected, indicating that
the received data input (UARTRXD input pin) was held LOW for
longer than a full-word transmission time (defined as start, data,
parity and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO (i.e., the oldest received data character since last read).
When a break occurs, a 0 character is loaded into the FIFO. The
next character is enabled after the receive data input (UARTRXD
input pin) goes to a 1 (marking state), and the next valid start bit is
received.
UART Parity Error:
When set to 1, it indicates that the parity of the received data
character does not match the parity that the LCRH.EPS and
LCRH.SPS select.
In FIFO mode, this error is associated with the character at the top of
the FIFO (i.e., the oldest received data character since last read).
SWCU117C – February 2015 – Revised September 2015
www.ti.com
19 18 17
3 2 1
DATA
R/W-X
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