Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1361

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Bit Field
4 RXIM
3-2 RESERVED
1 CTSMIM
0 RESERVED
SWCU117C – February 2015 – Revised September 2015
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Table 19-13. IMSC Register Field Descriptions (continued)
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Description
Receive interrupt mask. A read returns the current mask for the
UART receive interrupt. On a write of 1, the mask of the overrun
error interrupt is set which means the interrupt state will be reflected
in MIS.RXMIS. A write of 0 clears the mask, which means
MIS.RXMIS will not reflect the interrupt.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Clear to Send (CTS) modem interrupt mask. A read returns the
current mask for the UART clear to send interrupt. On a write of 1,
the mask of the overrun error interrupt is set which means the
interrupt state will be reflected in MIS.CTSMMIS. A write of 0 clears
the mask, which means MIS.CTSMMIS will not reflect the interrupt.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Universal Asynchronous Receivers and Transmitters (UARTS)
UARTS Registers
1361