Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1022

I/O Control Registers
11.11.3.29 IOCFG28 Register (Offset = 70h) [reset = 6000h]
IOCFG28 is shown in
Configuration of DIO28
31 30
RESERVED HYST_EN
R-0h R/W-0h
23 22
15 14
RESERVED PULL_CTL
R-0h
7 6
RESERVED
R-0h
Bit Field
31 RESERVED
30 HYST_EN
29 IE
28-27 WU_CFG
26-24 IOMODE
1022
I/O Control
Figure 11-51 and described in
Figure 11-51. IOCFG28 Register
29 28
IE
R/W-0h
21 20
RESERVED
R/W-0h
13 12
SLEW_RED
R/W-3h R/W-0h
5 4
Table 11-55. IOCFG28 Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 11-55.
27 26
WU_CFG
R/W-0h
19 18
EDGE_IRQ_EN
R/W-0h
11 10
IOCURR
R/W-0h
3 2
PORT_ID
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
0: Input hysteresis disable
1: Input hysteresis enable
0: Input disabled
1: Input enabled
Note: If IO is configured for AUX, that is PORT_ID = 0x08, the
enable will be ignored.
If DIO is configured GPIO or non-AON peripheral signals, that is
PORT_ID 0x00 or >0x08:
00: No wakeup
01: No wakeup
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.
If IO is configured for AON peripheral signals or AUX, that is
PORT_ID 0x01-0x08, this register only sets wakeup enable or not.
00, 01: Wakeup disabled
10, 11: Wakeup enabled
Polarity is controlled from AON registers.
Note: When the MSB is set, the IOC will deactivate the output
enable for the DIO.
IO Mode
N/A for IO configured for AON peripheral signals and AUX, that is
PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.
0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
0h = NORMAL : Normal input/output
1h = INV : Inverted input/output
4h = OPENDR : Open Drain,
Normal input/output
5h = OPENDR_INV : Open Drain
Inverted input/output
6h = OPENSRC : Open Source
Normal input/output
7h = OPENSRC_INV : Open Source
Inverted input/output
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
IOMODE
R/W-0h
17 16
EDGE_DET
R/W-0h
9 8
IOSTR
R/W-0h
1 0
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