Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1226

AUX – Sensor Controller Registers
17.7.1.8 ADC0 Register (Offset = 8h) [reset = 0h]
ADC0 is shown in
ADC Control 0
7 6
SMPL_MODE
R/W-0h
Bit Field
7 SMPL_MODE
6-3 SMPL_CYCLE_EXP
2 RESERVED
1 RESET_N
0 EN
1226
AUX – Sensor Controller with Digital and Analog Peripherals
Figure 17-10 and described in
Figure 17-10. ADC0 Register
5 4
SMPL_CYCLE_EXP
R/W-0h
Table 17-29. ADC0 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 17-29.
3 2
RESERVED
R/W-0h
Description
ADC Sampling mode:
0: Synchronous mode
1: Asynchronous mode
The ADC does a sample-and-hold before conversion. In
synchronous mode the sampling starts when the ADC clock detects
a rising edge on the trigger signal. Jitter/uncertainty will be inferred in
the detection if the trigger signal originates from a domain that is
asynchronous to the ADC clock. SMPL_CYCLE_EXP determines the
the duration of sampling.
Conversion starts immediately after sampling ends.
In asynchronous mode the sampling is continuous when enabled.
Sampling ends and conversion starts immediately with the rising
edge of the trigger signal. Sampling restarts when the conversion
has finished.
Asynchronous mode is useful when it is important to avoid jitter in
the sampling instant of an externally driven signal
Controls the sampling duration before conversion when the ADC is
operated in synchronous mode (SMPL_MODE = 0). The setting has
no effect in asynchronous mode. The sampling duration is given as
SMPL_CYCLE_EXP + 1
2 / 6 µs.
3h = 2P7_US : 16x 6 MHz clock periods = 2.7 µs
4h = 5P3_US : 32x 6 MHz clock periods = 5.3 µs
5h = 10P6_US : 64x 6 MHz clock periods = 10.6 µs
6h = 21P3_US : 128x 6 MHz clock periods = 21.3 µs
7h = 42P6_US : 256x 6 MHz clock periods = 42.6 µs
8h = 85P3_US : 512x 6 MHz clock periods = 85.3 µs
9h = 170_US : 1024x 6 MHz clock periods = 170 µs
Ah = 341_US : 2048x 6 MHz clock periods = 341 µs
Bh = 682_US : 4096x 6 MHz clock periods = 682 µs
Ch = 1P37_MS : 8192x 6 MHz clock periods = 1.37 ms
Dh = 2P73_MS : 16384x 6 MHz clock periods = 2.73 ms
Eh = 5P46_MS : 32768x 6 MHz clock periods = 5.46 ms
Fh = 10P9_MS : 65536x 6 MHz clock periods = 10.9 ms
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Reset ADC digital subchip, active low. ADC must be reset every time
it is reconfigured.
0: Reset
1: Normal operation
ADC Enable
0: Disable
1: Enable
SWCU117C – February 2015 – Revised September 2015
www.ti.com
1 0
RESET_N EN
R/W-0h R/W-0h
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