Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1197

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17.4.1.5.4 Arithmetic and Logical Operations
The arithmetic and logical operations operate on a destination operand in an integer register, while the
source can be either another integer register, or an 8-bit immediate operand.
Table 17-6 lists the arithmetic and logical instructions.
Syntax Description
Dyadic instructions
add Rd,#simm Add immediate
cmp Rd,#simm Compare immediate
and Rd,#imm AND immediate
or Rd,#imm OR immediate
xor Rd,#imm XOR immediate
tst Rd,#imm Test immediate
add Rd,Rs Add register
sub Rd,Rs Subtract register
subr Rd,Rs Subtract reverse register
cmp Rd,Rs Compare register
and Rd,Rs AND register
or Rd,Rs OR register
xor Rd,Rs XOR register
tst Rd,Rs Test register
Monadic instructions
abs Rd Absolute register
neg Rd Negate register
not Rd Invert register
(1)
Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)
For instructions using an immediate operand, an 8-bit immediate is embedded in the instruction word.
Using the prefix-instruction, the immediate can be extended to a full 16-bit.
The arithmetic add and cmp instructions treat the 8-bit immediate as a signed quantity, in other words in
the range of –128 to +127, sign-extending it to full register width as appropriate. This allows, for example,
immediate subtractions to be performed using the add instruction.
The logical and, or, xor, and tst instructions treat the 8-bit immediate as an unsigned quantity, in other
words in the range of 0 to 255, zero-extending it to full register width as appropriate.
For all operations, the zero (Z) flag is set if the result is 0. The negative (N) flag is set equal to the most
significant bit of the result.
For arithmetic operations, the carry (C) flag is set according to a carry or borrow out of the most significant
bit of the result. Similarly, the overflow (V) flag is asserted if a arithmetic signed overflow occurs.
For logical operations, the carry (C) and overflow (V) flags are always both cleared.
SWCU117C – February 2015 – Revised September 2015
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Table 17-6. Arithmetic and Logical Instructions
Operation
Rd += simm
Rd – simm
Rd &= imm
Rd |= imm
Rd ^= imm
Rd & imm
Rd += Rs
Rd –= Rs
Rd = Rs – Rd
Rd – Rs
Rd &= Rs
Rd |= Rs
Rd ^= Rs
Rd & Rs
Rd = Rd > 0 ? Rd : –Rd
Rd = –Rd
Rd = ~Rd
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(1)
Z N C
x x x
x x x
x x 0
x x 0
x x 0
x x 0
x x x
x x x
x x x
x x x
x x 0
x x 0
x x 0
x x 0
x x x
x x x
x x 0
Modules
V
x
x
0
0
0
0
x
x
x
x
0
0
0
0
x
x
0
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