www.ti.com
Bit
Field
8
FE
7-0
DATA
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Table 19-4. DR Register Field Descriptions (continued)
Type
Reset
R
X
R/W
X
Copyright © 2015, Texas Instruments Incorporated
Description
UART Framing Error:
When set to 1, it indicates that the received character did not have a
valid stop bit (a valid stop bit is 1).
In FIFO mode, this error is associated with the character at the top of
the FIFO (i.e., the oldest received data character since last read).
Data transmitted or received:
On writes, the transmit data character is pushed into the FIFO.
On reads, the oldest received data character since the last read is
returned.
Universal Asynchronous Receivers and Transmitters (UARTS)
UARTS Registers
1349