Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1468

I2S Registers
22.10.1.28 IRQFLAGS Register (Offset = 74h) [reset = 0h]
IRQFLAGS is shown in
Raw Interrupt Status Register
31 30
23 22
15 14
7 6
RESERVED
R-0h
Bit Field
31-6 RESERVED
5 AIF_DMA_IN
4 AIF_DMA_OUT
3 WCLK_TIMEOUT
2 BUS_ERR
1 WCLK_ERR
0 PTR_ERR
1468
Integrated Interchip Sound (I2S) Module
Figure 22-36 and described in
Figure 22-36. IRQFLAGS Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
AIF_DMA_IN AIF_DMA_OUT
R-0h R-0h
Table 22-29. IRQFLAGS Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 22-29.
27 26
19 18
11 10
3 2
WCLK_TIMEO BUS_ERR
UT
R-0h R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Set when condition for this bit field event occurs (auto cleared when
input pointer is updated - AIFINPTR), see description of AIFINPTR
register
Set when condition for this bit field event occurs (auto cleared when
output pointer is updated - AIFOUTPTR), see description of
AIFOUTPTR register for details
Set when the sample stamp generator does not detect a positive
WCLK edge for 65535 clk periods. This signalizes that the internal or
external BCLK and WCLK generator source has been disabled.
The bit is sticky and may only be cleared by software (by writing '1'
to IRQCLR.WCLK_TIMEOUT).
Set when a DMA operation is not completed in time (that is audio
output buffer underflow, or audio input buffer overflow).
This error requires a complete restart since word synchronization
has been lost. The bit is sticky and may only be cleared by software
(by writing '1' to IRQCLR.BUS_ERR).
Note that DMA initiated transactions to illegal addresses will not
trigger an interrupt. The response to such transactions is undefined.
Set when:
- An unexpected WCLK edge occurs during the data delay period of
a phase. Note unexpected WCLK edges during the word and idle
periods of the phase are not detected.
- In dual-phase mode, when two WCLK edges are less than 4 BCLK
cycles apart.
- In single-phase mode, when a WCLK pulse occurs before the last
channel.
This error requires a complete restart since word synchronization
has been lost. The bit is sticky and may only be cleared by software
(by writing '1' to IRQCLR.WCLK_ERR).
Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been
loaded with the next block address in time.
This error requires a complete restart since word synchronization
has been lost. The bit is sticky and may only be cleared by software
(by writing '1' to IRQCLR.PTR_ERR).
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
9 8
1 0
WCLK_ERR PTR_ERR
R-0h R-0h
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