Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1418

2
I C Registers
21.5.1.10 MSTAT Register (Offset = 804h) [reset = 20h]
MSTAT is shown in
Master Status
31 30
23 22
15 14
7 6
RESERVED BUSBSY
R-0h R-0h
Bit Field
31-7 RESERVED
6 BUSBSY
5 IDLE
4 ARBLST
3 DATACK_N
2 ADRACK_N
1 ERR
0 BUSY
1418
Inter-Integrated Circuit (I
Figure 21-23 and described in
Figure 21-23. MSTAT Register
29 28
21 20
13 12
5 4
IDLE ARBLST
R-1h R-0h
Table 21-12. MSTAT Register Field Descriptions
Type Reset
R 0h
R 0h
R 1h
R 0h
R 0h
R 0h
R 0h
R 0h
2
C) Interface
Copyright © 2015, Texas Instruments Incorporated
Table 21-12.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
DATACK_N ADRACK_N
R-0h R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Bus busy
0: The I2C bus is idle.
1: The I2C bus is busy.
The bit changes based on the MCTRL.START and MCTRL.STOP
conditions.
I2C idle
0: The I2C controller is not idle.
1: The I2C controller is idle.
Arbitration lost
0: The I2C controller won arbitration.
1: The I2C controller lost arbitration.
Data Was Not Acknowledge
0: The transmitted data was acknowledged.
1: The transmitted data was not acknowledged.
Address Was Not Acknowledge
0: The transmitted address was acknowledged.
1: The transmitted address was not acknowledged.
Error
0: No error was detected on the last operation.
1: An error occurred on the last operation.
I2C busy
0: The controller is idle.
1: The controller is busy.
When this bit-field is set, the other status bits are not valid.
Note: The I2C controller requires four SYSBUS clock cycles to
assert the BUSY status after I2C master operation has been initiated
through MCTRL register.
Hence after programming MCTRL register, application is requested
to wait for four SYSBUS clock cycles before issuing a controller
status inquiry through MSTAT register.
Any prior inquiry would result in wrong status being reported.
SWCU117C – February 2015 – Revised September 2015
26 25
18 17
10 9
2 1
ERR
R-0h
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24
16
8
0
BUSY
R-0h