Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1351

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19.7.1.3 ECR Register (Offset = 4h) [reset = 0h]
ECR is shown in Figure 19-6
Error Clear
This register is mapped to the same address as RSR register. Reads from this address are associated
with RSR register and return the receive status. Writes to this address are associated with ECR register
and clear the receive status flags (framing, parity, break, and overrun errors).
31 30 29 28
15 14 13 12
Bit Field
31-4 RESERVED
3 OE
2 BE
1 PE
0 FE
SWCU117C – February 2015 – Revised September 2015
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and described in Table
Figure 19-6. ECR Register
27 26 25 24
RESERVED
W-0h
11 10 9 8
RESERVED
W-0h
Table 19-6. ECR Register Field Descriptions
Type Reset
W 0h
W 0h
W 0h
W 0h
W 0h
Copyright © 2015, Texas Instruments Incorporated
19-6.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
The framing (FE), parity (PE), break (BE) and overrun (OE) errors
are cleared to 0 by any write to this register.
The framing (FE), parity (PE), break (BE) and overrun (OE) errors
are cleared to 0 by any write to this register.
The framing (FE), parity (PE), break (BE) and overrun (OE) errors
are cleared to 0 by any write to this register.
The framing (FE), parity (PE), break (BE) and overrun (OE) errors
are cleared to 0 by any write to this register.
Universal Asynchronous Receivers and Transmitters (UARTS)
UARTS Registers
19 18 17 16
3 2 1 0
OE BE PE FE
W-0h W-0h W-0h W-0h
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