Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1374

Functional Description
Figure 20-3 shows the TI synchronous serial frame format when back-to-back frames are transmitted.
Figure 20-3. TI Synchronous Serial Frame Format (Continuous Transfer)
SSIn_Tx/SSIn_Rx
20.4.4.2 Motorola SPI Frame Format
The Motorola SPI interface is a 4-wire interface where the SSIn_FSS signal behaves as a slave select.
The main feature of the Motorola SPI format is that the inactive state and phase of the SSIn_CLK signal
can be programmed through the SPO and SPH bits in the SSI:CR0 control register.
20.4.4.2.1 SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, the bit produces a steady-state low value on the
SSIn_CLK pin. If the SPO bit is set, the bit places a steady-state high value on the SSIn_CLK pin when
data is not being transferred.
20.4.4.2.2 SPH Phase-Control Bit
The SPH phase-control bit selects the clock edge that captures data, and allows it to change state. The
state of this bit has the most impact on the first bit transmitted, by either allowing or not allowing a clock
transition before the first data capture edge. When the SPH phase-control bit is clear, data is captured on
the first clock edge transition. If the SPH bit is set, data is captured on the second clock edge transition.
20.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
Figure 20-4 and Figure 20-5
format with SPO = 0 and SPH = 0, respectively.
Figure 20-4. Motorola SPI Format (Single Transfer) With SPO = 0 and SPH = 0
SSIn_Clk
SSn_IFss
SSIn_Rx
SSIn_Tx
Note: Q is undefined.
1374
Synchronous Serial Interface (SSI)
SSIn_Clk
SSIn_Fss
show single and continuous transmission signal sequences for Motorola SPI
MSB
MSB
Copyright © 2015, Texas Instruments Incorporated
LSB
4 to 16 bits
4 to 16 bits
SWCU117C – February 2015 – Revised September 2015
www.ti.com
LSB Q
LSB
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