Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1459

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22.10.1.19 STMPOUTTRIG Register (Offset = 4Ch) [reset = 0h]
STMPOUTTRIG is shown in
WCLK Counter Trigger Value for Output Pins
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bit Field
31-16 RESERVED
15-0 OUT_START_WCNT
SWCU117C – February 2015 – Revised September 2015
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Figure 22-27 and described in
Figure 22-27. STMPOUTTRIG Register
R-0h
Table 22-20. STMPOUTTRIG Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 22-20.
9
OUT_START_WCNT
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Compare value used to start the outgoing audio streams.
This bit field must equal the WCLK counter value during the WCLK
period in which the first output word(s) read from memory are
clocked out (that is the sample at the start of the very first DMA
output buffer).
The value of this register takes effect when the following conditions
are met:
- One or more pins are configured as outputs in AIFDIRCFG.
- AIFDMACFG has been configured for the correct buffer size, and
32 BCLK cycle ticks have happened.
- 2 samples have been preloaded from memory (examine the
AIFOUTPTR register if necessary).
Note: The memory read access is only performed when required,
that is channels 0/1 must be selected in AIFWMASK0/AIFWMASK1.
Note: To avoid false triggers, this bit field must be set higher than
STMPWPER.VALUE.
Integrated Interchip Sound (I2S) Module
I2S Registers
8 7 6 5 4 3 2 1 0
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