Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1388

SSI Registers
20.7.1.5 CPSR Register (Offset = 10h) [reset = 0h]
CPSR is shown in
Clock Prescale
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-8 RESERVED
7-0 CPSDVSR
1388
Synchronous Serial Interface (SSI)
Figure 20-17 and described in
Figure 20-17. CPSR Register
RESERVED
R-0h
Table 20-7. CPSR Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 20-7.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Clock prescale divisor:
This field specifies the division factor by which the input system
clock to SSI must be internally divided before further use.
The value programmed into this field must be an even nonzero
number (2-254). The least significant bit of the programmed number
is hard-coded to zero. If an odd number is written to this register,
data read back from
this register has the least significant bit as zero.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8 7 6 5 4 3 2 1
CPSDVSR
R/W-0h
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