Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1153

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15.4.1.6 MIS Register (Offset = 14h) [reset = 0h]
MIS is shown in Figure 15-7
Masked Interrupt Status
31 30
23 22
15 14
7 6
Bit Field
31-1 RESERVED
0 WDTMIS
SWCU117C – February 2015 – Revised September 2015
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and described in Table 15-7.
Figure 15-7. MIS Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 15-7. MIS Register Field Descriptions
Type Reset Description
R 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R 0h This register is the masked interrupt status register. The value of this
register is the logical AND of the raw interrupt bit and the WDT
interrupt enable bit CTL.INTEN.
Value Description
0: The WDT has not timed out or is masked.
1: An unmasked WDT time-out event has occurred.
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27 26
19 18
11 10
3 2
Watchdog Timer Registers
25 24
17 16
9 8
1 0
WDTMIS
R-0h
1153
Watchdog Timer