Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1390

Zigbee rf4ce wireless mcu simplelink cc13 series; simplelink cc26 series

SSI Registers

20.7.1.7 RIS Register (Offset = 18h) [reset = 8h]

RIS is shown in

Figure 20-19

Raw Interrupt Status

Synchronous Serial Interface (SSI)

and described in

Figure 20-19. RIS Register

Table 20-9. RIS Register Field Descriptions

Software must not rely on the value of a reserved. Writing any other

value than the reset value may result in undefined behavior.

Raw transmit FIFO interrupt status:

The transmit interrupt is asserted when there are four or fewer valid

entries in the transmit FIFO. The transmit interrupt is not qualified

with the SSI enable signal. Therefore one of the following ways can

- data can be written to the transmit FIFO prior to enabling the SSI

- SSI and interrupts can be enabled so that data can be written to

the transmit FIFO by an interrupt service routine.

Raw interrupt state of receive FIFO interrupt:

The receive interrupt is asserted when there are four or more valid

entries in the receive FIFO.

Raw interrupt state of receive timeout interrupt:

The receive timeout interrupt is asserted when the receive FIFO is

not empty and SSI has remained idle for a fixed 32 bit period. This

mechanism can be used to notify the user that data is still present in

the receive FIFO and requires servicing. This interrupt is deasserted

if the receive FIFO becomes empty by subsequent reads, or if new

data is received on RXD.

It can also be cleared by writing to ICR.RTIC.

Raw interrupt state of receive overrun interrupt:

The receive overrun interrupt is asserted when the FIFO is already

full and an additional data frame is received, causing an overrun of

the FIFO. Data is over-written in the

receive shift register, but not the FIFO so the FIFO contents stay

It can also be cleared by writing to ICR.RORIC.

SWCU117C – February 2015 – Revised September 2015

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