Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1136

Real-Time Clock Registers
14.4.1.5 SUBSECINC Register (Offset = 10h) [reset = 800000h]
SUBSECINC is shown in
Subseconds Increment
Value added to SUBSEC.VALUE on every **SCLK_LF ** clock cycle.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
R-0h
Bit Field
31-24 RESERVED
23-0 VALUEINC
1136
Real-Time Clock
Figure 14-6 and described in
Figure 14-6. SUBSECINC Register
Table 14-6. SUBSECINC Register Field Descriptions
Type Reset
R 0h
R 800000h
Copyright © 2015, Texas Instruments Incorporated
Table 14-6.
9
VALUEINC
R-800000h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
This value compensates for a SCLK_LF clock which has an offset
from 32768 Hz.
The compensation value can be found as 2
SCLK_LF clock frequency in Hertz
This value is added to SUBSEC.VALUE on every cycle, and carry of
this is added to SEC.VALUE. To perform the addition, bits [23:6] are
aligned with SUBSEC.VALUE bits [17:0]. The remaining bits [5:0]
are accumulated in a hidden 6-bit register that generates a carry into
the above mentioned addition on overflow.
The default value corresponds to incrementing by precisely 1/32768
of a second.
NOTE: This register is read only. Modification of the register value
must be done using registers AUX_WUC:RTCSUBSECINC1,
AUX_WUC:RTCSUBSECINC0 and
AUX_WUC:RTCSUBSECINCCTL.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8 7 6 5 4 3 2 1
38
/ freq, where freq is
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