Texas Instruments SimpleLink CC2620 Technical Reference Manual page 861

www.ti.com
10.2.1.30 AESDATAIN3 Register (Offset = 56Ch) [reset = 0h]
AESDATAIN3 is shown in
Data Input/Output
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-0 DATA
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Figure 10-32 and described in
Figure 10-32. AESDATAIN3 Register
DATA
W-0h
Table 10-40. AESDATAIN3 Register Field Descriptions
Type Reset
W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 10-40.
9
Description
Data registers for input block data to the Crypto peripheral.
These bits = AES Input Data[127:96] of [127:0]
For normal operations, this register is not used because data input
and output is transferred from and to the AES engine through DMA.
For a Host write operation, these registers must be written with the
128-bit input block for the next AES operation. Writing at a word-
aligned offset within this address range will store the word (4 bytes)
of data into the corresponding position of 4-word deep (16 bytes =
128-bit AES block) data input buffer. This buffer is used for the next
AES operation. If the last data block is not completely filled with valid
data (see notes below), it is allowed to write only the words with valid
data. Next AES operation is triggered by writing to
AESCTL.INPUT_RDY.
Note: AES typically operates on 128 bits block multiple input data.
The CTR, GCM and CCM modes form an exception. The last block
of a CTR-mode message may contain less than 128 bits (refer to
[NIST 800-38A]): 0 < n <= 128 bits. For GCM/CCM, the last block of
both AAD and message data may contain less than 128 bits (refer to
[NIST 800-38D]). The Crypto peripheral automatically pads or masks
misaligned ending data blocks with zeroes for GCM, CCM and CBC-
MAC. For CTR mode, the remaining data in an unaligned data block
is ignored.
Cryptography Registers
8 7 6 5 4 3 2 1 0
861