Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1423

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21.5.1.14 MIMR Register (Offset = 810h) [reset = 0h]
MIMR is shown in
Master Interrupt Mask
This register controls whether a raw interrupt is promoted to a controller interrupt.
31 30 29 28
15 14 13 12
Bit Field
31-1 RESERVED
0 IM
SWCU117C – February 2015 – Revised September 2015
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Figure 21-27 and described in
Figure 21-27. MIMR Register
27 26 25
11 10 9
RESERVED
Table 21-16. MIMR Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 21-16.
24 23 22 21
RESERVED
R-0h
8 7 6 5
R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Interrupt mask
0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt
controller.
1: The master interrupt is sent to the interrupt controller when the
MRIS.RIS is set.
0h = Disable Interrupt
1h = Enable Interrupt
I
20 19 18 17
4 3 2
2
Inter-Integrated Circuit (I C) Interface
2
C Registers
16
1 0
IM
R/W-
0h
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