Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1413

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21.5.1.5 SIMR Register (Offset = Ch) [reset = 0h]
SIMR is shown in Figure 21-18
Slave Interrupt Mask
This register controls whether a raw interrupt is promoted to a controller interrupt.
31 30
23 22
15 14
7 6
Bit Field
31-3 RESERVED
2 STOPIM
1 STARTIM
0 DATAIM
SWCU117C – February 2015 – Revised September 2015
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and described in
Figure 21-18. SIMR Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 21-7. SIMR Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 21-7.
27 26
19 18
11 10
3 2
STOPIM
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Stop condition interrupt mask
0: The SRIS.STOPRIS interrupt is suppressed and not sent to the
interrupt controller.
1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt
controller.
0h = Disable Interrupt
1h = Enable Interrupt
Start condition interrupt mask
0: The SRIS.STARTRIS interrupt is suppressed and not sent to the
interrupt controller.
1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt
controller.
0h = Disable Interrupt
1h = Enable Interrupt
Data interrupt mask
0: The SRIS.DATARIS interrupt is suppressed and not sent to the
interrupt controller.
1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt
controller.
Inter-Integrated Circuit (I
2
I C Registers
25 24
17 16
9 8
1 0
STARTIM DATAIM
R/W-0h R/W-0h
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2
C) Interface