Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1084

Zigbee rf4ce wireless mcu simplelink cc13 series; simplelink cc26 series

Functional Description

Table 13-5. Counter Values When the Timer is Enabled in PWM Mode

When software writes to the GPT:CTL TnEN register bit, the counter begins counting down until it reaches

the 0x0 state. Alternatively, if the GPT:TnMR TnWOT register bit is set when the TnEN bit is set, the timer

waits for a trigger to begin counting. On the next counter cycle in periodic mode, the counter reloads its

start value from the GPT:TnILR and the GPT:TnPR registers, and continues counting until disabled by

software clearing the GPT:CTL TnEN register bit. The timer is capable of generating interrupts based on

three types of events: rising edge, falling edge, or both. The event is configured by the GPT:CTL

TnEVENT register field, and the interrupt is enabled by setting the GPT:TnMR TnPWMIE register bit.

When the event occurs, the GPTM Raw Interrupt Status Register (GPT:RIS) CnERIS bit is set, and holds

the bit until it is cleared by writing the GPTM Interrupt Clear Register (GPT:ICLR). If the capture mode

event interrupt is enabled in the GPTM Interrupt Mask Register (GPT:IMR), the GPTM also sets the

GPTM Masked Interrupt Status Register (GPT:MIS) CnEMIS bit.

NOTE: The interrupt status bits are not updated unless the TnPWMIE bit is set.

In the PWM mode, the GPT:TnR and the GPT:TnV registers always have the same value, as do the

GPT:PnPS and the GPT:TnPV registers.

The output PWM signal asserts when the counter is at the value of the GPT:TnILR and the GPT:TnPR

registers (its start state), and is deasserted when the counter value equals the value in the

GPT:TnMATCHR and the GPT:TnPMR registers. Software can invert the output PWM signal by setting

the GPT:CTL TnPWML register bit. Inverting the output PWM does not affect the edge detection interrupt.

Therefore, if a positive-edge interrupt trigger has been set, the event-trigger interrupt is asserted when the

PWM inversion generates a positive edge.

shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a

50-MHz input clock and TnPWML = 0 (duty cycle would be 33% for the TnPWML = 1 configuration). For

this example, the start value is GPT:TnILR = 0xC350 and the match value is GPT:TnMATCHR = 0x411A.

Count Down Mode

Count Up Mode

Not Available

SWCU117C – February 2015 – Revised September 2015

Submit Documentation Feedback

Show Quick Links