Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1109

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13.5.1.13 TBMATCHR Register (Offset = 34h) [reset = FFFFh]
TBMATCHR is shown in
Timer B Match Register
When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded
into the upper 16 bits of TAMATCHR.
Reads from this register return the current match value of Timer B and writes are ignored.
In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases.
Note : This register is updated internally (takes effect) based on TBMR.TBMRSU
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bit Field
31-16 RESERVED
15-0 TBMATCHR
SWCU117C – February 2015 – Revised September 2015
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Figure 13-21 and described in
Figure 13-21. TBMATCHR Register
R-0h
Table 13-20. TBMATCHR Register Field Descriptions
Type Reset
R 0h
R/W FFFFh
Copyright © 2015, Texas Instruments Incorporated
Table 13-20.
9
TBMATCHR
R/W-FFFFh
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
GPT Timer B Match Register
General-purpose Timer Registers
8 7 6 5 4 3 2 1
Timers
0
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