Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1425

www.ti.com
21.5.1.16 MMIS Register (Offset = 818h) [reset = 0h]
MMIS is shown in
Master Masked Interrupt Status
This register show which interrupt is active (based on result from MRIS and MIMR).
31 30 29 28
15 14 13 12
Bit Field
31-1 RESERVED
0 MIS
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Figure 21-29 and described in
Figure 21-29. MMIS Register
27 26 25
11 10 9
RESERVED
Table 21-18. MMIS Register Field Descriptions
Type Reset
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 21-18.
24 23 22 21
RESERVED
R-0h
8 7 6 5
R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Masked interrupt status
0: An interrupt has not occurred or is masked.
1: A master interrupt is pending.
This bit is cleared by writing 1 to the MICR.IC bit .
I
20 19 18 17
4 3 2
2
Inter-Integrated Circuit (I C) Interface
2
C Registers
16
1 0
MIS
R-0h
1425