Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1397

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When operating in slave mode, 2 bits in the I
detection of Start and Stop conditions on the bus, while 2 bits in the I
I2C:SMIS register allow promotion of Start and Stop conditions to controller interrupts (when interrupts are
enabled).
21.3.1.2 Data Format With 7-bit Address
Data transfers follow the format shown in
transmitted. This address is 7 bits long followed by an eighth bit, which is a data direction bit (the R/S bit
in the I2C:MSA register). If the RS bit is clear, it indicates a transmit operation (send), and if it is set, it
indicates a request for data (receive). A data transfer is always terminated by a Stop condition generated
by the master; however, a master can initiate communications with another device on the bus, by
generating a Repeated Start condition and addressing another slave without first generating a Stop
condition. Various combinations of receive and transmit formats are then possible within a single transfer.
SDA
SCL
Start
The first 7 bits of the first byte comprise the slave address (see
the direction of the message. A 0 in the R/S position of the first byte means that the master transmits
(sends) data to the selected slave, and a 1 in this position means that the master receives data from the
slave.
21.3.1.3 Data Validity
The SDA line must contain stable data during the high period of the clock, and the data line can change
only when SCL is low (see
Figure 21-6. Data Validity During Bit Transfer on the I
21.3.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle generated by the master. During the
acknowledge cycle, the transmitter (master or slave) releases the SDA line. To acknowledge the
transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data transmitted by
the receiver during the acknowledge cycle must comply with the data validity requirements described in
Section 21.3.1.3, Data Validity.
When a slave receiver does not acknowledge the slave address, the slave must leave SDA high so that
the master can generate a Stop condition and abort the current transfer. If the master device is acting as a
receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Because
the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter
by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to
let the master generate a Stop or a Repeated Start condition.
SWCU117C – February 2015 – Revised September 2015
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Figure
Figure 21-4. Complete Data Transfer With a 7-bit Address
MSB LSB R/S
1 2 7 8
Slave address
Figure 21-5. R/S Bit in First Byte
MSB
Slave address
Figure 21-6).
SDA
SCL
Data line
stable
Copyright © 2015, Texas Instruments Incorporated
2
C Slave Raw Interrupt Status I2C:SRIS register indicate
2
C Slave Masked Interrupt Status
21-4. After the Start condition, a slave address is
ACK MSB
9 1 2 7
Data
Figure
LSB
R/S
Change
of data
allow
Functional Description
LSB ACK
8 9
Stop
21-5). The eighth bit determines
2
C Bus
2
Inter-Integrated Circuit (I C) Interface
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