Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1085

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0xC350
0x411A
TnPWML = 0
Output
Signal
TnPWML = 1
When synchronizing the timers using the GPT:SYNC register, the timer must be properly configured to
avoid glitches on the CCP outputs. Both the TnPLO and the TnMRSU bits must be set in the GPT:TnMR
register. Figure 13-5
the GPT:TnMATCHR register value is greater than the GPT:TnILR register value.
Figure 13-6 shows how the CCP output operates when the PLO and MRSU bits are set and the
GPT:TnMATCHR register value is the same as the GPT:TnILR register value. In this situation, if the PLO
bit is 0, the CCP signal goes high when the GPT:TnILR register value is loaded, and the match would be
essentially ignored.
SWCU117C – February 2015 – Revised September 2015
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Figure 13-4. 16-bit PWM Mode Example
Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
TnEN set
shows how the CCP output operates when the TnPLO and TnMRSU bits are set and
Figure 13-5. CCP Output, GPT:TnMATCHR > GPT:TnILR
GPTMnILR
CCP
CCP set if GPTMnMATCHR
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GPTMnMATCHR
GPTMnILR
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Functional Description
Time
1085
Timers