Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1154

Watchdog Timer Registers
15.4.1.7 TEST Register (Offset = 418h) [reset = 0h]
TEST is shown in
Test Mode
31 30
23 22
15 14
7 6
Bit Field
31-9 RESERVED
8 STALL
7-1 RESERVED
0 TEST_EN
1154
Watchdog Timer
Figure 15-8 and described in
Figure 15-8. TEST Register
29 28
21 20
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 15-8. TEST Register Field Descriptions
Type Reset
R 0h
R/W 0h
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 15-8.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
3
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
WDT Stall Enable
0: The WDT timer continues counting if the CPU is stopped with a
debugger.
1: If the CPU is stopped with a debugger, the WDT stops counting.
Once the CPU is restarted, the WDT resumes counting.
0h = Disable STALL
1h = Enable STALL
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
The test enable bit
0: Enable external reset
1: Disables the generation of an external reset. Instead bit 1 of the
INT_CAUS register is set and an interrupt is generated
0h = Test mode Disabled
1h = Test mode Enabled
SWCU117C – February 2015 – Revised September 2015
26 25
18 17
10 9
2 1
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24
16
8
STALL
R/W-0h
0
TEST_EN
R/W-0h