Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1096

General-purpose Timer Registers
Bit Field
8 TBILD
7 TBSNAPS
6 TBWOT
5 TBMIE
4 TBCDIR
3 TBAMS
2 TBCM
1-0 TBMR
1096
Timers
Table 13-10. TBMR Register Field Descriptions (continued)
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Description
GPT Timer B PWM Interval Load Write
0h = Update the TBR register with the value in the TBILR register on
the next clock cycle. If the pre-scaler is used, update the TBPS
register with the value in the TBPR register on the next clock cycle.
1h = Update the TBR register with the value in the TBILR register on
the next timeout. If the prescaler is used, update the TBPS register
with the value in the TBPR register on the next timeout.
GPT Timer B Snap-Shot Mode
0h = Snap-shot mode is disabled.
1h = If Timer B is configured in the periodic mode
GPT Timer B Wait-On-Trigger
0h = Timer B begins counting as soon as it is enabled.
1h = If Timer B is enabled (CTL.TBEN is set), Timer B does not
begin counting until it receives a trigger from the timer in the
previous position in the daisy chain.
GPT Timer B Match Interrupt Enable.
0h = The match interrupt is disabled for match events. Additionally,
output triggers on match events are prevented.
1h = An interrupt is generated when the match value in the
TBMATCHR register is reached in the one-shot and periodic modes.
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0h = DOWN : The timer counts down.
1h = UP : The timer counts up. When counting up, the timer starts
from a value of 0x0.
GPT Timer B Alternate Mode
Note: To enable PWM mode, you must also clear TBCM bit and
configure TBMR field to 0x2.
0h = Capture/Compare mode is enabled.
1h = PWM mode is enabled
GPT Timer B Capture Mode
0h = EDGCNT : Edge-Count mode
1h = EDGTIME : Edge-Time mode
GPT Timer B Mode
The Timer mode is based on the timer configuration defined by
CFG.CFG
1h = One-Shot Timer mode
2h = Periodic Timer mode
3h = Capture mode
SWCU117C – February 2015 – Revised September 2015
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