Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1350

UARTS Registers
19.7.1.2 RSR Register (Offset = 4h) [reset = 0h]
RSR is shown in Figure 19-5
Status
This register is mapped to the same address as ECR register. Reads from this address are associated
with RSR register and return the receive status. Writes to this address are associated with ECR register
and clear the receive status flags (framing, parity, break, and overrun errors).
If the status is read from this register, then the status information for break, framing and parity
corresponds to the data character read from the Data Register, DR prior to reading the RSR. The status
information for overrun is set immediately when an overrun condition occurs.
31 30 29 28
15 14 13 12
Bit Field
31-4 RESERVED
3 OE
2 BE
1 PE
0 FE
1350
Universal Asynchronous Receivers and Transmitters (UARTS)
and described in Table
Figure 19-5. RSR Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
RESERVED
R-0h
Table 19-5. RSR Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
19-5.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
UART Overrun Error:
This bit is set to 1 if data is received and the receive FIFO is already
full. The FIFO contents remain valid because no more data is written
when the FIFO is full, , only the contents of the shift register are
overwritten.
This is cleared to 0 once there is an empty space in the FIFO and a
new character can be written to it.
UART Break Error:
This bit is set to 1 if a break condition was detected, indicating that
the received data input (UARTRXD input pin) was held LOW for
longer than a full-word transmission time (defined as start, data,
parity and stop bits).
When a break occurs, a 0 character is loaded into the FIFO. The
next character is enabled after the receive data input (UARTRXD
input pin) goes to a 1 (marking state), and the next valid start bit is
received.
UART Parity Error:
When set to 1, it indicates that the parity of the received data
character does not match the parity that the LCRH.EPS and
LCRH.SPS select.
UART Framing Error:
When set to 1, it indicates that the received character did not have a
valid stop bit (a valid stop bit is 1).
SWCU117C – February 2015 – Revised September 2015
www.ti.com
19 18 17 16
3 2 1 0
OE BE PE FE
R-0h R-0h R-0h R-0h
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