Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1375

Zigbee rf4ce wireless mcu simplelink cc13 series; simplelink cc26 series

Figure 20-5. Motorola SPI Format (Continuous Transfer) With SPO = 0 and SPH = 0

In this configuration, the following occurs during idle periods:

SSIn_CLK is forced low

SSIn_FSS is forced high

The transmit data line SSIn_TX is arbitrarily forced low

When the SSI is configured as a master, it enables the SSIn_CLK pad

When the SSI is configured as a slave, it disables the SSIn_CLK pad

If the SSI is enabled and valid data is in the TX FIFO, the SSIn_FSS master signal is driven low at the

start of transmission which causes enabling of slave data onto the SSIn_RX input line of the master. The

master SSIn_TX output pad is enabled.

One-half SSIn_CLK period later, valid master data is transferred to the SSIn_TX pin. Once both the

master and slave data are set, the SSIn_CLK master clock pin goes high after an additional one-half

SSIn_CLK period.

The data is now captured on the rising edges and propagated on the falling edges of the SSIn_CLK

For a single-word transmission after all bits of the data word are transferred, the SSIn_FSS line is returned

to its IDLE high state one SSIn_CLK period after the last bit is captured.

For continuous back-to-back transmissions, the SSIn_FSS signal must pulse high between each data

word transfer because the slave-select pin freezes the data in its serial peripheral register and does not

allow altering of the data if the SPH bit is clear. The master device must raise the SSIn_FSS pin of the

slave device between each data transfer to enable the serial peripheral data write. When the continuous

transfer completes, the SSIn_FSS pin is returned to its IDLE state one SSIn_CLK period after the last bit

is captured.

SWCU117C – February 2015 – Revised September 2015

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Synchronous Serial Interface (SSI)

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